FPL 2023

Tutorial: Introduction to Vendor-Independent Model-Based Design for FPGAs

Organizers:

• Dimitri Hamidi is Senior Application Engineer at MathWorks since 2018, with a focus on HDL code generation and verification, as well as signal and image processing. He received a diploma degree in electrical and information technology engineering from the Technical University of Munich. Prior to joining MathWorks, he worked as a research associate at the German Aerospace Center (DLR), served as FPGA engineer at FEI and algorithm engineer at Continental. 

• Daniel Aronsson is an application engineer at MathWorks with specialization in signal processing and communications system design. He has several years of experience in these fields, and he also works regularly with deep learning and FPGA/ASIC design and verification. Daniel holds a Ph.D. in wireless communications from Uppsala University, on the topic of MIMO channel prediction.

• Håkan Pettersson is a senior application engineer at MathWorks, focusing on ASIC/FPGA implementation and verification workflows but also on CI/CD workflows using cloud. Håkan has been with MathWorks for 5 years, and prior to this worked with one of the major EDA tool vendors focusing on synthesis and verification for ASIC/FPGA.  

Date: 04 Sep 2023, 13:30-17:30 CET

Location: Scania Floor plan

More than two-thirds of all FPGA and ASIC projects are behind schedule. Over half of the development effort is verification while debugging accounts for a quarter of the project time. Nonetheless, over 80% of all FPGA projects have non-trivial bug escapes into production, also in safety-critical applications. The main root causes are design errors (specifications implemented incorrectly) or incorrect, incomplete, and changing specifications. Those issues can be attributed to the shortcomings of traditional design and verification methodologies based on translating textual requirements and behavioral specification models into RTL code and test benches manually.

Model-based digital hardware design addresses effectively the above problems. Multidomain modeling and simulation enable cross-domain collaboration and help to converge on a complete and consistent executable system specification. A large pre-verified library supporting different applications such as signal processing, computer vision, and communications cuts development costs. Generation of bit and cycle true HDL from digital components ensures that the RTL fulfills its specification and reduces debugging effort. Model testbenches are reused automatically to verify RTL. This ultimately results in accelerated design cycles, fast reaction time to changing specifications, and higher product quality and safety. Moreover, any FPGA or ASIC can be targeted. This integrated workflow has been adopted by leading companies and certified by TUV SUD for usage in automotive, medical, railway, and other safety-critical domains.

This tutorial will cover the process of designing, simulating, and analyzing digital hardware using MATLAB, Simulink, and Stateflow. The attendees will learn how to generate bit-true, cycle-accurate, readable Verilog and VHDL code for different implementation architectures. They will also delve into optimizing fixed-point data types, resources, and timing for production. Next, the tutorial will also highlight the importance of establishing requirement traceability for ensuring implementation completeness. It will, then, demonstrate to the attendees creating test harnesses, managing test benches, and linking them to test requirements. They will learn how to prove the completeness of tests and detect dead logic using model coverage techniques. An introduction to verifying RTL with auto-generated SystemVerilog test benches, co-simulation, and FPGA-in-the-Loop will also be given. Lastly, they demonstration will be given on how to generate IP Cores with AXI interfaces and deploy algorithms on a Xilinx SoC for live audio processing.

Tutorial: Co-Designing Compute Architectures That Can Accelerate Neural Networks Using FINN

Organizers: Michaela Blott (Senior Fellow and head of AMD Research, Ireland); Thomas Preusser (Senior Staff Machine Learning Engineer at AMD Research, Germany); Jakoba Petri-Koenig (Research Engineer at AMD Research, Ireland); Zaid Al-Ars (Associate Professor at Delft University of Technology, Netherlands)

Tutorial: Introduction to the Versal ACAP AI Engine and to its Programming Model

Organizers: Mario Ruiz (AMD University Program, AMD, Ireland); Cathal McCabe (AMD University Program, AMD, Ireland)

Date: 05 Sep 2023, 08:30-17:30 CET

Location: Scania Floor plan

With the decline of Moore’s law, HPC systems need to include specialized heterogeneous accelerators to continue performance scaling. FPGAs are emerging as an ideal target for a range of applications. This tutorial will briefly introduce the heterogeneous AMD’s Versal Adaptive Compute Acceleration Platform (ACAP). We will primarily focus on the Adaptable Intelligent Engine (AIE), a new type of compute element in the latest AMD technology. The AI Engines are a tiled array of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provide high compute density.

In this tutorial we will describe the AI Engine tile and array architecture as well as the different connectivity methods. We will also have an introduction to AI Engine programming which consists of a Data Flow Graph Specification written in C++ and the kernel description, written either in C or C++. The application can be compiled and executed using the AI Engine tool chain, which is part of the Vitis Unified Software platform that enables the user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems.

Tutorial: RVfpga: Understanding Computer Architecture

Organizers: Robert C.W. Owen (Imagination University Programme); Daniel A. Chaver-Martinez (Associate Professor, Department of Computer Architecture, University Complutense of Madrid, Spain); Olof Kindgren (Senior Digital-Design Engineer at Qamcom, Sweden)

Date: 05 Sep 2023, 08:30-12:30 CET

Location: Valdemar and Ledningsrummet Floor plan

Imagination Technologies offers a tutorial on the RISC-V Computer Architecture, called RISC-V FPGA or simply RVfpga, to be used by university teachers, professors, and related industry members. The materials can be downloaded for free from: https://university.imgtec.com/rvfpga/.

The tutorial explores the fundamentals of computer architecture using the open-source, commercial VeeR (originally called SweRV) EH1 RISC-V core targeted to Digilent’s Nexys A7 development board and to several simulation tools. In the tutorial, we will, first, show how to quickly get the RISC-V system and RISC-V tools up and running. Then, we will describe all of the RVfpga labs and show how to use and work through a selection of the hands-on labs. We will also discuss how to integrate RVfpga into your curriculum.

Tutorial: Network and Memory Abstractions on FPGAs for Distributed Applications

Organizers: Dario Korolija (doctoral student at Systems Group, Department of Computer Science, ETH Zurich, Switzerland); Zhenhao He (doctoral student at Systems Group, Department of Computer Science, ETH Zurich, Switzerland); Gustavo Alonso (professor at Systems Group, Department of Computer Science, ETH Zurich, Switzerland)

Date: 05 Sep 2023, 13:30-17:30 CET

Website: https://systems.ethz.ch/research/data-processing-on-modern-hardware/hacc/tutorial-fpl-2023.html

Location: Valdemar and Ledningsrummet Floor plan

FPGAs are increasingly being deployed in hybrid computing systems in the data centers in a variety of different configurations (e.g., Microsoft Catapult). Such a rapid cloud development makes FPGAs no longer viewed as a slave PCIe-attached accelerator, but as a first-class compute resource directly connected to the network. This opens up lots of opportunities for in-network processing and distributed computing on FPGAs. To fully harness the potential of FPGAs in data centers, it is crucial to address memory virtualization, networking, and resource sharing aspects. These factors play a pivotal role in accommodating diverse applications running in the cloud. However, the availability of comprehensive open-source infrastructure and resources providing a complete stack of abstraction layers is highly limited. Consequently, insufficient attention has been given to utilizing FPGAs in data center scenarios to tackle larger problems and support large-scale deployments.

In this tutorial, we will introduce several open-source resources that facilitate memory and network abstractions on FPGAs for distributed applications built on FPGA clusters. First, we present Coyote, a configurable FPGA shell that provides a set of traditional OS abstractions which virtualize the available FPGA resources, enabling both spatial and temporal multiplexing of FPGA applications. Coyote also provides a range of memory and networking services, a prerequisite for large-scale distributed applications. As a second step, we focus on hardware network stacks, e.g., TCP/IP stack with EasyNet and RDMA stack with Coyote, comparable in performance to standard data center infrastructures. As a third step, we present ACCL, an open-source MPI implementation for FPGAs developed to provide higher level of network abstraction and to simplify the use of networking in machine learning applications. We provide examples of real- world applications that can benefit from executing on network- attached FPGAs in areas like data analytics and machine learning.

In this tutorial, we present not only the design of such resources, but also how to deploy them in the AMD-ETHZ HACC heterogeneous compute cluster, which offers researchers worldwide the opportunity to pursue distributed processing research with network-attached FPGAs.

Workshop: FPGA4QC: 1st Workshop on FPGA Technology for Quantum Computing

Organizers: Pedro Trancoso (Chalmers University of Technology, Sweden); Martin Schulz (Technical University of Munich, Germany)