Date: 04 Sep 2023, 13:30-17:30 CET
Location: Scania Floor plan
More than two-thirds of all FPGA and ASIC projects are behind schedule. Over half of the development effort is verification while debugging accounts for a quarter of the project time. Nonetheless, over 80% of all FPGA projects have non-trivial bug escapes into production, also in safety-critical applications. The main root causes are design errors (specifications implemented incorrectly) or incorrect, incomplete, and changing specifications. Those issues can be attributed to the shortcomings of traditional design and verification methodologies based on translating textual requirements and behavioral specification models into RTL code and test benches manually.
Model-based digital hardware design addresses effectively the above problems. Multidomain modeling and simulation enable cross-domain collaboration and help to converge on a complete and consistent executable system specification. A large pre-verified library supporting different applications such as signal processing, computer vision, and communications cuts development costs. Generation of bit and cycle true HDL from digital components ensures that the RTL fulfills its specification and reduces debugging effort. Model testbenches are reused automatically to verify RTL. This ultimately results in accelerated design cycles, fast reaction time to changing specifications, and higher product quality and safety. Moreover, any FPGA or ASIC can be targeted. This integrated workflow has been adopted by leading companies and certified by TUV SUD for usage in automotive, medical, railway, and other safety-critical domains.
This tutorial will cover the process of designing, simulating, and analyzing digital hardware using MATLAB, Simulink, and Stateflow. The attendees will learn how to generate bit-true, cycle-accurate, readable Verilog and VHDL code for different implementation architectures. They will also delve into optimizing fixed-point data types, resources, and timing for production. Next, the tutorial will also highlight the importance of establishing requirement traceability for ensuring implementation completeness. It will, then, demonstrate to the attendees creating test harnesses, managing test benches, and linking them to test requirements. They will learn how to prove the completeness of tests and detect dead logic using model coverage techniques. An introduction to verifying RTL with auto-generated SystemVerilog test benches, co-simulation, and FPGA-in-the-Loop will also be given. Lastly, they demonstration will be given on how to generate IP Cores with AXI interfaces and deploy algorithms on a Xilinx SoC for live audio processing.