FPL 2023
CONFERENCE PROGRAM
Program Overview
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Monday Sep 4
13:00-13:30 Registrations Open
Location: Entrance Foyer 📍Floor plan
Tuesday Sep 5
08:00-08:30 Registrations Open
Location: Entrance Foyer 📍Floor plan
Wednesday Sep 6
08:00-08:30 Registrations Open
Location: Entrance Foyer 📍Floor plan
08:30-08:45 Opening
Location: RunAn 📍Floor plan
08:45-09:40 Keynote I : Kunle Olukotun, Professor, Stanford
Reconfigurable Dataflow Accelerators for the Foundation Model Era Abstract Slides
Location: RunAn 📍Floor plan
Session Chair: Ioannis Sourdis (Chalmers University of Technology)
09:40-10:40 Session 1 : Tools I
Location: RunAn 📍Floor plan
Session Chair: Thomas Preusser (AMD)
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis ⭐ Michal Servit Award winner
Robert Szafarczyk (University of Glasgow, UK), Syed Waqar Nabi (University of Glasgow, UK), Wim Vanderbauwhede (University of Glasgow, UK)
Fortran High Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs
Gabriel Rodriguez-Canal (The University of Edinburgh), Nick Brown (The University of Edinburgh), Tim Dykes (HPC/AI EMEA Research Lab, Hewlett Packard Enterprise), Jess Jones (HPC/AI EMEA Research Lab, Hewlett Packard Enterprise), Utz-Uwe Haus (HPC/AI EMEA Research Lab, Hewlett Packard Enterprise)
An Open-Source Framework for Efficient Numerically-Tailored Computations
Louis Ledoux (Universitat Politecnica de Catalunya (UPC)), Marc Casas (Universitat Politecnica de Catalunya (UPC))
09:40-10:40 Research Projects Event
Location: Scaniasalen 📍Floor plan
Session Chair: João MP Cardoso (University of Porto)
High-Level Synthesis of Complex Space Applications in the context of the EU-HERMES project Slides
Project: HERMES, Speaker: Fabrizio Ferrandi (Politecnico di Milano)
Accelerators for Heterogenous Computing in AIoT Slides
Project: VEDLIoT, Speaker: René Griessl (Universität Bielefeld)
Distributed Shared Memory Multi-FPGA Platform for eFlows4HPC Project Slides
Project: eFlows4HPC, Speaker: David Rodríguez Agut (Universitat Politècnica de València)
Automatic system-level design for reconfigurable HPC applications: The EVEREST approach Slides
Project: EVEREST, Speaker: Christian Pilato (Politecnico di Milano)
10:40-11:10 Coffee Break
Location: Volvo Foyer 📍Floor plan
11:10-12:30 Session 2 : Hardware for Deep Learning
Location: RunAn 📍Floor plan
Session Chair: Dirk Stroobandt (Ghent University)
An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-oriented Pruning
Shiqing Li (Nanyang Technological University, Singapore), Shien Zhu (Nanyang Technological University, Singapore), Xiangzhong Luo (Nanyang Technological University, Singapore), Tao Luo (Institute of High Performance Computing, Agency for Science Technology and Research (A*STAR), Singapore), Weichen Liu (Nanyang Technological University, Singapore)
Token-packing for Transformers with Variable-Length Inputs
Tiandong Zhao (University of California, Los Angeles, USA), Siyuan Miao (University of California, Los Angeles, USA), Shaoqiang Lu (Eastern Institute of Advanced Study, China), Jialin Cao (Fudan University, China), Jun Qiu (Southeast University, China), Xiao Shi (Southeast University, China), Kun Wang (Fudan University, China), Lei He (Eastern Institute of Advanced Study, China; University of California, Los Angeles, USA)
HPTA: A High Performance Transformer Accelerator Based on FPGA Stamatis Vassiliadis Award candidate
Yuntao Han (Tianjin University, China), Qiang Liu (Tianjin University, China)
HyperGRAF: Hyperdimensional Graph-based Reasoning Acceleration on FPGA Stamatis Vassiliadis Award candidate
Hanning Chen (University of California, Irvine, USA), Ali Zakeri (University of California, Irvine, USA), Fei Wen (Texas A&M University, USA), Hamza Errahmouni Barkam (University of California, Irvine, USA), Mohsen Imani (University of California, Irvine, USA)
11:10-12:30 Research Projects Event
Location: Scaniasalen 📍Floor plan
Session Chair: Cristina Silvano (Politecnico di Milano)
Energy-Efficient AI in the Data Center by Approximating DNNs for FPGAs (eki) Slides
Project: eki, Speaker: Marco Platzner (Universität Paderborn)
Energy-Efficient Machine Learning Inference via FPGA-Emulated Neuromorphic Architectures Slides
Project: ACROSS, Speaker: Paolo Savio (LINKS Foundation)
Highly Efficient Residual Networks for FPGA Slides
Project: ICSC - EDA tools, Speaker: Urso Teodoro (Politecnico di Torino)
Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms: An Early Survey Slides
Project: ICSC - DL Accelerators, Speaker: Stefania Perri (Università della Calabria)
Dynamic Memory Expansion with Hardware-Accelerated Compression Slides
Project: Vitamin-V, Speaker: Angelos Arelakis (ZeroPoint Technologies Corp.)
12:30-13:30 Lunch
Location: Volvo Foyer 📍Floor plan
13:30-14:20 Keynote II : Nabeel Shirazi, Intel
Grand Challenges for FPGAs in the Next Decade Abstract Slides
Location: RunAn 📍Floor plan
Session Chair: Leonel Sousa (Universidade de Lisboa)
14:20-16:00 Session 3 : Tools II
Location: RunAn 📍Floor plan
Session Chair: Marco Platzner (University of Paderborn)
Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture Michal Servit Award candidate
Kimia Talaei Khoozani (University of Toronto, Canada), Arash Ahmadian Dehkordi (University of Toronto, Canada), Vaughn Betz (University of Toronto, Canada)
SPADES: A Productive Design flow for Versal Programmable Logic
Tan Nguyen (UC Berkeley), Zachary Blair (AMD), Stephen Neuendorffer (AMD), John Wawrzynek (UC Berkeley)
VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization
Ruichen Chen (University of Alberta, Canada), Shengyao Lu (University of Alberta, Canada), Mohamed A. Elgammal (University of Toronto, Canada), Peter Chun (University of Alberta, Canada), Vaughn Betz (University of Toronto, Canada), Di Niu (University of Alberta, Canada)
Automated Masking of FPGA-Mapped Designs
Nicolai Müller (Ruhr University Bochum, Germany), Sergej Meschkov (Karlsruhe Institute of Technology, Germany), Dennis R. E. Gnad (Karlsruhe Institute of Technology, Germany), Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany), Amir Moradi (Ruhr University Bochum, Germany)
fpgaHART: A toolflow for throughput-oriented acceleration of 3D CNNs for HAR onto FPGAs
Petros Toupas (Imperial College London; Information Technologies Institute, Centre of Research and Technology Hellas), Christos-Savvas Bouganis (Imperial College London), Dimitrios Tzovaras (Information Technologies Institute, Centre of Research and Technology Hellas)
14:20-16:00 Industrial Event
Location: Scaniasalen 📍Floor plan
Session Chair: Tobias Becker (Maxeler Technologies, UK) and Melina Demertzi (ZeroPoint, Sweden)
Introducing the new AMD University Program
Speaker: Mario Noguera Ruiz (AMD)
Designing a RISC-V SoC with the NOEL-V Processor and the GRLIB IP Library
Speaker: Jan Andersson (Frontgrade Gaisler)
Adding an energy and performance-efficient hardware tier to CXL memory expansion
Speaker: Angelos Arelakis (ZeroPoint)
Intel FPGA AI Suite
Speaker: Johan Bernspang (Intel)
SERV: 32-bit is the new 8-bit
Speaker: Olof Kingdren (Qamcom)
GroqChip: A new Generation of Real-time AI
Speaker: Tobias Becker (Maxeler)
The Power of FPGAs in Heterogeneous Computing - Scalable Computing from Cloud to IoT
Speaker: Rene Griessl (Christmann)
16:00-18:00 PhD Forum
Location: Volvo Foyer 📍Floor plan
Session Chair: Dirk Koch (Heidelberg University, Germany) and Vassilis Papaefstathiou (FORTH-ICS, Greece)
Exploring FPGA Acceleration for Distributed Serverless Computing
Ziyi Yang (King Abdullah University of Science and Technology (KAUST), Saudi Arabia), Suhaib A. Fahmy (King Abdullah University of Science and Technology (KAUST), Saudi Arabia)
Challenges using FPGA Clusters for Distributed CNN Training
Philipp Kreowsky (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute; University of Potsdam, Germany), Justin Knapheide (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute; University of Potsdam, Germany), Benno Stabernack (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute; University of Potsdam, Germany)
Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs
Rubén Macias (Complutense University of Madrid, Spain), Sergio Bernabé (Complutense University of Madrid, Spain), Carlos González (Complutense University of Madrid, Spain)
Building a Reusable and Extensible Automatic Compiler Infrastructure for reconfigurable devices
Zhenya Zang (Codeplay Software Ltd.; Edinburgh Napier University, United Kindom), Uwe Dolinsky (Codeplay Software Ltd., United Kindom), Pietro Ghiglio (Codeplay Software Ltd., United Kindom), Stefano Cherubin (Edinburgh Napier University, United Kindom), Mehdi Goli (Codeplay Software Ltd., United Kindom), Shufan Yang (Edinburgh Napier University, United Kindom)
A Scalable and Cross-Technology Quantum Control Processor
Xiaorang Guo (Technical University of Munich, Germany), Martin Schulz (Technical University of Munich, Germany)
Bayesian Optimization for Efficient Heterogeneous MPSoC based DNN Accelerator Runtime Tuning
Xuqi Zhu (University of Essex, United Kingdom), Cong Gao (University of Essex, United Kingdom), Sangeet Saha (University of Essex, United Kingdom), Xiaojun Zhai (University of Essex, United Kingdom), Klaus D McDonald-Maier (University of Essex, United Kingdom)
Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems
Veronia Iskandar (Technische Universität Dresden, Germany), Mohamed A. Abd El Ghany (German University in Cairo, Egypt; TU Darmstadt, Germany), Diana Goehringer (Technische Universität Dresden; Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Germany)
Hardware-aware AutoML for Exploration of Custom FPGA Accelerators for RadioML
Felix Jentzsch (Paderborn University, Germany)
Towards Coarse-Grained Reconfigurable Approximate Computing with CGRAgen
Hans Jakob Damsgaard (Tampere University, Finland), Aleksandr Ometov (Tampere University, Finland), Jari Nurmi (Tampere University, Finland)
16:00-18:00 Demo Night
Location: Volvo Foyer 📍Floor plan
Session Chair: Dirk Koch (Heidelberg University, Germany) and Vassilis Papaefstathiou (FORTH-ICS, Greece)
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters
Justin Knapheide (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute; University of Potsdam, Germany), Philipp Kreowsky (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute; University of Potsdam, Germany), Benno Stabernack (Fraunhofer Institute for Telecommunications, Heinrich Hertz Institute, University of Potsdam, Germany)
HashCache: High-Performance State Tracking for Resilient FPGA-based Packet Processing
Michael Offel (Synogate UG, Germany), Andreas Ley (Synogate UG, Germany), Sven Hager (Synogate UG, Germany)
FABulous demo: Open Source FPGA on Sky130
Myrtle Shah (Heidelberg University), Jakob Ternes (Heidelberg University), Dirk Koch (Heidelberg University)
FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms
Yunyi Zhao (University College London, UK), Yunjia Xia (University College London, UK), Rui Loureiro (University College London, UK), Hubin Zhao (University College London, UK), Uwe Dolinsky (Codeplay Software Ltd, UK), Shufan Yang (Edinburgh Napier University, UK)
Thursday Sep 7
08:30-09:00 Registrations Open
Location: Entrance Foyer 📍Floor plan
09:00-09:50 Keynote III : Arvind, Professor, CSAIL, MIT
Computing Near Storage Abstract Slides
Location: RunAn 📍Floor plan
Session Chair: Pedro Trancoso (Chalmers University of Technology)
09:50-10:30 Session 4 : Applications
Location: RunAn 📍Floor plan
Session Chair: Cristina Silvano (Politecnico di Milano)
Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse ⭐Stamatis Vassiliadis Award winner
Haishuang Fan (Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences), Jiangya Wu (Institute of Computing Technology, Chinese Academy of Sciences), Wenyan Lu (Institute of Computing Technology, Chinese Academy of Sciences), Xiaowei Li (Institute of Computing Technology, Chinese Academy of Sciences), Guihai Yan (Institute of Computing Technology, Chinese Academy of Sciences)
FSSD: FPGA-based Emulator for SSDs
Luyang Yu (University of Illinois Urbana-Champaign), Yizhen Lu (University of Illinois Urbana-Champaign), Meghna Mandava (University of Illinois Urbana-Champaign), Edward Richter (University of Illinois Urbana-Champaign), Vikram Sharma Mailthody (NVIDIA), Seung Won Min (University of Illinois Urbana-Champaign), Wen-mei Hwu (University of Illinois Urbana-Champaign), Deming Chen (University of Illinois Urbana-Champaign)
10:30-10:40 Posters Pitch
Session Chair: Pedro Trancoso (Chalmers University of Technology)
Location: Volvo Foyer 📍Floor plan
10:40-11:10 Coffee Break | Poster Presentations
Location: Volvo Foyer 📍Floor plan
11:10-12:30 Session 5 : Configurable Architectures
Location: RunAn 📍Floor plan
Session Chair: João Cardoso (University of Porto)
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
MD Arafat Kabir (University of Arkansas), Ehsan Kabir (University of Arkansas), Joshua Hollis (University of Arkansas), Eli Levy-Mackay (University of Arkansas), Atiyehsadat Panahi (Cadence Design Systems), Jason Bakos (University of South Carolina), Miaoqing Huang (University of Arkansas), David Andrews (University of Arkansas)
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture
Pengyu Liu (Shanghai Jiao Tong University, China), Zihan Zhang (Shanghai Jiao Tong University, China), Chen Yin (Shanghai Jiao Tong University, China), Liyan Chen (Shanghai Jiao Tong University, China), Jianfei Jiang (Shanghai Jiao Tong University, China), Qin Wang (Shanghai Jiao Tong University, China), Zhigang Mao (Shanghai Jiao Tong University, China), Naifeng Jing (Shanghai Jiao Tong University, China)
Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs
Shaden Alismail (The University of Manchester, UK; Imam Mohammad Ibn Saud Islamic University, Saudi Arabia), Dirk Koch (The University of Manchester, UK; Heidelberg University, Germany)
Tear Down The Wall: Unified and Efficient Intra- and Inter-Cluster Routing for FPGAs
Amin Mohaghegh (University of Toronto, Canada), Vaughn Betz (University of Toronto, Canada)
12:30-13:30 Lunch
Location: Volvo Foyer 📍Floor plan
13:30-14:50 Session 6 : Numerical Analysis
Location: RunAn 📍Floor plan
Session Chair: Deming Chen (University of Illinois at Urbana-Champaign)
Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs
Garcia Rémi (Nantes Université, France), Volkova Anastasia (Nantes Université, France)
Optimization Techniques for Hestenes-Jacobi SVD on FPGAs
Lukas Stasytis (Technical University of Darmstadt, Germany), Zsolt István (Technical University of Darmstadt, Germany)
Accelerating SpMV on FPGAs through block-row compress: a task-based approach
José Oliver (Barcelona Supercomputing Center; Universitat Politècnica de Catalunya, Spain), Carlos Álvarez (Barcelona Supercomputing Center; Universitat Politècnica de Catalunya, Spain), Teresa Cervero (Barcelona Supercomputing Center, Spain), Xavier Martorell (Barcelona Supercomputing Center; Universitat Politècnica de Catalunya, Spain), John D. Davis (Barcelona Supercomputing Center, Spain), Eduard Ayguadé (Barcelona Supercomputing Center; Universitat Politècnica de Catalunya, Spain)
MSDF-SGD: Most-significant Digit-first Stochastic Gradient Descent for Arbitrary-precision Training
Changjun Song (Southeast University, China), Yongming Tang (Southeast University, China), Jiyuan Liu (Southeast University, China), Sige Bian (Southeast University, China), Danni Deng (Southeast University, China), He Li (Southeast University, China)
14:50-15:00 Posters Pitch
Session Chair: Pedro Trancoso (Chalmers University of Technology)
Location: Volvo Foyer 📍Floor plan
15:00-15:50 Coffee Break | Poster Presentations
Location: Volvo Foyer 📍Floor plan
15:50-17:30 Session 7 : Hardware Accelerators
Location: RunAn 📍Floor plan
Session Chair: Jason Anderson (University of Toronto)
DiAD- Distributed Acceleration for Datacenter FPGAs
Joshua Lant (University of Manchester, UK), Emmanouil Skordalakis (University of Manchester, UK), Kyriakos Paraskevas (University of Manchester, UK), William B. Toms (University of Manchester, UK), Mikel Luján (University of Manchester, UK), John Goodacre (University of Manchester, UK)
FPGA Acceleration of Rotation in Homomorphic Encryption using Dynamic Data Layout
Yang Yang (University of Southern California), Weihang Long (Tsinghua University), Rajgopal Kannan (DEVCOM Army Research Lab), Viktor K. Prasanna (University of Southern California)
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization
Ce Guo (Imperial College London, United Kingdom), Diego Cupello (Imperial College London, United Kingdom), Wayne Luk (Imperial College London, United Kingdom), Joshua Levine (Intel, United Kingdom), Alexander Warren (Intel, United Kingdom), Peter Brookes (Intel, United Kingdom)
SPEAR-JSON: Selective parsing of JSON to enable accelerated stream processing on FPGAs
Tobias Hahn (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany), Stefan Wildermann (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany), Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany)
A Novel Hardware Accelerator of NeRF based on Xilinx UltraScale and UltraScale+ FPGA
Baoze Zhao (Sun Yat-sen University, China), Wenjin Huang (Sun Yat-sen University, China), Yihua Huang (Sun Yat-sen University; Southern Marine Science and Engineering Guangdong Laboratory, China)
Friday Sep 8
08:30-09:00 Registrations Open
Location: Entrance Foyer 📍Floor plan
09:00-09:50 Keynote V : Trevor Bauer, AMD
Adaptive Architectures for Efficient Compute Abstract Slides
Location: RunAn 📍Floor plan
Session Chair: Nele Mentens (Leiden University and KU Leuven)
09:50-10:20 Coffee Break | Poster Presentations
Location: Volvo Foyer 📍Floor plan
10:20-12:00 Session 8 : Neural Networks I
Location: RunAn 📍Floor plan
Session Chair: Luigi Carro (Instituto de Informatica / UFRGS)
Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition
Zhewen Yu (Imperial College London, UK), Christos-Savvas Bouganis (Imperial College London, UK)
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization ⭐FPL Community Award Winner
Stefan Abi-Karam (Georgia Institute of Technology; Georgia Tech Research Institute), Cong Hao (Georgia Institute of Technology)
Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
Paul Chen (University of Southern California, USA), Pavan Manjunath (University of Southern California, USA), Sasindu Wijeratne (University of Southern California, USA), Bingyi Zhang (University of Southern California, USA), Viktor Prasanna (University of Southern California, USA)
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks
Ruiqi Chen (Fudan University, China), Haoyang Zhang (Fudan University, China), Shun Li (Fuzhou University, China), Enhao Tang (Fuzhou University, China), Jun Yu (Fudan University, China), Kun Wang (Fudan University, China)
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
Shashwat Khandelwal (Trinity College Dublin, Ireland), Shanker Shreejith (Trinity College Dublin, Ireland)
12:00-13:00 Lunch
Location: Volvo Foyer 📍Floor plan
13:00-14:40 Session 9 : TRETS
Location: RunAn 📍Floor plan
Session Chair: Christian Pilato (Politecnico di Milano)'
Reprogrammable non-linear circuits using ReRAM for NN accelerators
Rafael de Moura (Federal University of Rio Grande do Sul); Luigi Carro (Federal University of Rio Grande do Sul)
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm
John Kalomiros (International Hellenic University); John Vourvoulakis (International Hellenic University); Stavros Vologiannidis (International Hellenic University)
FDRA: A Framework for Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism
Yunhui Qiu (Fudan University); Yiqing Mao (Fudan University); Xuchen Gao (Fudan University); Sichao Chen (Fudan University); Wenbo Yin (Fudan University); Lingli Wang (Fudan University)
Strega: An HTTP Server for FPGAs
Fabio Maschi (ETH Zurich); Gustavo Alonso (ETH Zurich)
Programmable Analog System Benchmarks leading to Efficient Analog Computation Synthesis
Jennifer Hasler (Georgia Institute of Technology); Cong Hao (Georgia Institute of Technology)
14:40-14:55 Closing
Location: RunAn 📍Floor plan
Posters and Exhibition
Calabash: Accelerating Attention using a Systolic Array Chain on FPGAs
Zizhang Luo (Peking University), Liqiang Lu (Zejiang University), Yichen Jin (Duke University), Liancheng Jia (Peking University), Yun Liang (Peking University)
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration
Zhiqiang Que (Imperial College London, UK), Shuo Liu (Imperial College London, UK), Markus Rognlien (Imperial College London, UK), Ce Guo (Imperial College London, UK), Jose G. F. Coutinho (Imperial College London, UK), Wayne Luk (Imperial College London, UK)
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center
Mohammadmahdi Mazraeli (University of Toronto, Canada), Yu Gao (University of Toronto, Canada), Paul Chow (University of Toronto, Canada)
Remote Identification of Neural Network FPGA Accelerators by Power Fingerprints
Vincent Meyers (Karlsruhe Institute of Technology (KIT), Germany), Michael Hefenbrock (RevoAI GmbH, Germany), Dennis Gnad (Karlsruhe Institute of Technology (KIT), Germany), Mehdi Tahoori (Karlsruhe Institute of Technology (KIT), Germany)
A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices?
Andrew Boutros (University of Toronto, Canada), Stephen More (University of Toronto, Canada), Vaughn Betz (University of Toronto, Canada)
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning
Huimin Li (Delft University of Technology, The Netherlands), Phillip Rieger (Technical Universität Darmstadt, Germany), Shaza Zeitouni (Technical Universität Darmstadt, Germany), Stjepan Picek (Radboud University; Delft University of Technology, The Netherlands), Ahmad-Reza Sadeghi (Technical Universität Darmstadt, Germany)
eGPU: A 750 MHz Class Soft GPGPU for FPGA
Martin Langhammer (Intel Corporation; Imperial College London), George A. Constantinides (Imperial College)
LTrans-OPU: A Low-Latency FPGA-based Overlay Processor for Transformer Networks Acceleration
Yueyin Bai (Fudan University, China), Hao Zhou (Fudan University, China), Keqing Zhao (Fudan University, China), Manting Zhang (Fudan University, China), Jianli Chen (Fudan University, China), Jun Yu (Fudan University, China), Kun Wang (Fudan University, China)
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
Alexander Montgomerie-Corcoran (Imperial College London, UK), Zhewen Yu (Imperial College London, UK), Jianyi Cheng (Imperial College London, UK), Christos-Savvas Bouganis (Imperial College London, UK)
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs
Shi-Yu Huang (National Yang Ming Chiao Tung University, Taiwan), Yun-Chen Yang (National Yang Ming Chiao Tung University, Taiwan), Yu-Ru Su (National Yang Ming Chiao Tung University, Taiwan), Bo-Cheng Lai (National Yang Ming Chiao Tung University, Taiwan), Javier Duarte (University of California, USA), Scott Hauck (University of Washington, USA), Shih-Chieh Hsu (University of Washington, USA), Jin-Xuan Hu (National Yang Ming Chiao Tung University, Taiwan), Mark S. Neubauer (University of Illinois at Urbana-Champaign, USA)
Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs
Vaibhav Kashera (IIIT Hyderabad, India), Siddhant Jain (IIIT Hyderabad, India), Abhishek Banerjee (Lotusdew, India), Suresh Purini (IIIT Hyderabad, India)
GRAMM: Fast CGRA Application Mapping Based on a Heuristic for Finding Graph Minors
Guanglei Zhou (University of Toronto, Canada), Mirjana Stojilović (EPFL, Switzerland), Jason H. Anderson (University of Toronto, Canada)
Improving the Reliability of FPGA CRO PUFs
Hayden Cook (Brigham Young University, USA), Zephram Tripp (Brigham Young University, USA), Brad Hutchings (Brigham Young University, USA), Jeffrey Goeders (Brigham Young University, USA)
FPGA Accelerating Multi-source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-coupled Receptors
Ruiqi Chen (Fudan University, China), Haoyang Zhang (Fudan University, China), Jun Yu (Fudan University, China), Kun Wang (Fudan University, China)
DIF-LUT: A Simple Yet Scalable Approximation for Non-linear Activation Function on FPGA
Yang Liu (Fudan University, China), Xiaoming He (Fudan University, China), Jun Yu (Fudan University, China), Kun Wang (Fudan University, China)
Accelerating High-Rate Dynamic Systems with LSTM Networks
Ehsan Kabir (University of Arkansas, USA), Daniel Coble (University of South Carolina, USA), Joud N. Satme (University of South Carolina, USA), Austin R.J. Downey (University of South Carolina, USA), Jason D. Bakos (University of South Carolina, USA), David Andrews (University of Arkansas, USA), Miaoqing Huang (University of Arkansas, USA)
Stress-resiliency of AI implementations on FPGAs
Jonas Krautter (Karlsruhe Institute of Technology (KIT), Germany), Paul R. Genssler (University of Stuttgart, Germany), Gloria Sepanta (University of Stuttgart, Germany), Hussam Amrouch (University of Stuttgart; Technical University of Munich (TUM); Munich Institute of Robotics and Machine Intelligence (MIRMI)), Mehdi Tahoori (Karlsruhe Institute of Technology (KIT), Germany)
A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAs
Christoph Niemann (University of Rostock, Germany), Michael Rethfeldt (University of Rostock, Germany), Dirk Timmermann (University of Rostock, Germany)